Synopsys and TSMC have expanded their partnership to support the design of next-generation AI and high-performance computing (HPC) chips across advanced semiconductor nodes, including TSMC’s 3nm and 2nm process families, A16 with Super Power Rail, and A14 technologies. The announcement covers silicon-proven IP, certified AI-driven EDA flows, and system-level design enablement for increasingly complex AI workloads.
The collaboration also includes support for advanced packaging technologies and multi-die architectures used in AI accelerators and data-center systems. Synopsys stated that its interface, foundation, and embedded memory IP solutions have been optimized for TSMC’s latest manufacturing processes, while certified EDA flows are intended to help address power, performance, and scalability requirements in AI chip development.
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