Keysight Technologies and Rambus have announced a collaboration focused on identifying side-channel leakage in AES (Advanced Encryption Standard) hardware designs during the pre-silicon stage. The approach aims to help semiconductor designers detect potential security vulnerabilities before chip fabrication by using simulation-based analysis alongside traditional post-silicon testing.
According to the companies, the methodology was evaluated on a pre-release Rambus AES implementation, where it reportedly identified the known leakage along with its root cause, with detection reported as consistent across RTL and gate-level simulations, and results aligning closely with earlier hardware-based measurements. The collaboration reflects a broader industry emphasis on integrating hardware security validation earlier in the semiconductor design process.
Image courtesy: Keysight Technologies