• Ansys Webinar: Accelerating ESD Simulation for Full-Chip and Multi-Die 3D-IC Design

    Join the PathFinder-SC webinar to learn about early pre-LVS ESD checks, cloud-native designs, and layout-based debugging to accelerate signoff and enhance design reliability. What Attendees Will Learn: Cell-based modeling of clamps from GDS/OASIS and/or P&R tool DEF/LEF Overview of static ESD simulation checks handled by PathFinder-SC for fullchip, interposer and multi-die designs Performance overview and […]

  • Synopsys Converge Conference: Re-engineering the Future

    Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, California (CA), United States

    Synopsys Converge 2026 is a premier technology conference bringing together industry leaders, engineers, and innovators to explore the future of semiconductor design, AI-driven engineering, and advanced systems development. The event features keynote sessions, technical talks, and live demonstrations on topics such as chip design, electronic design automation, simulation technologies, and intelligent system innovation, providing a […]

  • Mathworks webinar: Shortening Semiconductor Design Cycles

    The webinar Shortening Semiconductor Design Cycles with Early Modeling and Verification covers the role of MATLAB and Simulink in early-stage semiconductor IP modeling. It highlights applications in signal processing, mixed-signal systems, and high-speed serial interfaces, and reviews simulation and verification methods used before RTL and SPICE implementation. The session also explores how architectural models can […]