Ansys Webinar: Accelerating ESD Simulation for Full-Chip and Multi-Die 3D-IC Design

Join the PathFinder-SC webinar to learn about early pre-LVS ESD checks, cloud-native designs, and layout-based debugging to accelerate signoff and enhance design reliability.

What Attendees Will Learn:

• Cell-based modeling of clamps from GDS/OASIS and/or P&R tool DEF/LEF
• Overview of static ESD simulation checks handled by PathFinder-SC for fullchip, interposer and multi-die designs
• Performance overview and future road map sharing
• Debug and diagnostic capabilities