Cadence has introduced a fully autonomous virtual AI engineer for chip design and verification, developed using its ChipStack AI Super Agent framework and NVIDIA technologies. Described as operating at Level-5 autonomy, the system is designed to execute semiconductor design workflows with minimal human intervention, including specification analysis, RTL generation, verification planning, formal analysis, simulation, debugging, and design convergence.
Built on Cadence’s electronic design automation (EDA) portfolio, the AI agent uses NVIDIA Nemotron models and operates within the NVIDIA OpenShell runtime to support security, governance, and protection of sensitive design data. Early-access deployment is planned for the second half of 2026.
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